Training » Cortex™-M4, M3, M1, M0 (ARM): Architecture and Embedded Programming

Cortex™-M4, M3, M1, M0 (ARM):
Architecture and Embedded Programming

Training Objectives

You know the Cortex™-M4, M3, M1, M0 architecture and can write software in C and Assembler. You can place the programs in memory and test them. You get the perfect introduction in developing Cortex™-M based systems.

Required Knowhow

A basic understanding of ANSI-C and microcontrollers.

Cortex™-M4, M3, M1, M0 (ARMv7-M) Processor Architecture
- Register organization, special purpose register
- Operation modes (handler/thread, privileged/unprivileged)
- Main stack, process stack
- Cortex™-M pipeline concept
- Cortex™-M memory map, system control block, bit banding

ARM Processor Cores - Overview
- Cortex M0, M1, M3, M4, R4, A8, A9
- ARM7/9/10/11

Cortex™-M4, M3, M1, M0 Instruction Set
- Thumb-2 instruction set
- Data processing instructions
- Branch and control flow instructions, subroutines
- Branch table, if ... then conditional blocks
- Data access instructions
- Assembler directives

Exception and Interrupt Handling
- Exception model
- Reset, NMI, faults, SysTick, debug, supervisor calls, external interrupts
- Tail chaining, late arriving
- Nested vector interrupt controller (NVIC)
- Interrupt configuration and status
- Interrupt prioritization, priority grouping

Reset Modes, Clock Generation, Power Management
- Clock generation
- Resets and Cortex™-M reset modes
- Power management
- System timer

Memory Interface
- Bus interfaces for: AMBA 3 bus, instruction/data memories,
system interface, external private peripherals

Memory Protection Unit MPU for Embedded Systems

Embedded Core Debugging
- Core and system debugging
- JTAG debug port
- 2-pin single wire debug port
- Trace port interface unit
- Embedded trace macrocell

Embedded Software Development
- Adjustment of library routines to hardware (retargeting)
- Placing code and data in memory (scatter loading)
- Linker description files
- Processor start-up, start-up file

Efficient C Programming for Cortex Architectures
- Compiler optimization, compiler options
- Interface C - Assembler
- Programming guidelines for Cortex compilers
- Optimized utilization of local and global data

Hardware-near C
- C statements and their execution in Assembler
- Access to peripherals in C
- Software architecture for embedded systems
- Structured description of peripherals
- Cortex Microcontroller Software Interface Standard (CMSIS)

Floating Point Unit, Digital Signal Processing

Practical Exercises with Keil µVision and ARM RealView Tools
- Exercises - key issues of the Cortex™-M4, M3, M1, M0 architecture
- All programs are tested on an evaluation board using a Cortex controller of the
NXP LPC1700 family or STMicroelectronics STM32 family
- Alternative tools can be used on request

EXTRA

All participants get a FREE Nuvoton Cortex-M0 Development Kit
(NuMicro-SDK)!

Dates	Price plus VAT	Short Code	Duration
ON REQUEST	2,150 €	E-CORTEXMX	4 days
To register for this training, please download our Training Registration Form