Training » TriCore®: Architecture, Peripherals and Embedded Programming

TriCore®:
Architecture, Peripherals and Embedded Programming

Training Objectives

You know the architecture, basic on-chip periphery and specifics of the TriCore® device family. You are able to program low-level drivers for this hardware and test them with a debugger. Moreover, you can generate interrupt and trap routines.

Required Knowledge

Knowledge of ANSI-C as well as experience with programming and the set-up of a microprocessor/microcontroller system. Knowledge of DSP is an advantage.

Infineon TriCore® Architecture: Overview

TriCore® Core
- CPU, pipelines, register sets
- Memory model, Local Memory Units, MMU, FPU
- Overview instruction set, DSP support
- On-chip bus systems

TriCore® Ports (Pin Definition and Port Functions)

Hardware-near C with Tasking tools or HighTec GNU tools
- Architecture-specific data types
- Global data handling

Programming Techniques (Periphery Description, Layer Model)
- Description of periphery
- Layer model for embedded software systems

Driver Programming (Driver Model, LLD)
- Structured driver model
- Low-level driver LLD

Protection System

Interrupt/TRAP System

Peripheral Control Processor PCP2: Overview

Direct Memory Access Controller DMA: Overview

Basic On-Chip Peripherals
- Ports, timer: STM, RTC
- Serial interfaces: ASCx, SSCx

System Control Unit SCU, Reset, Power Management
- Start-up process
- System Control Unit (SCU)
- Resets (Power-on, HW, SW, WDT, Deep-Sleep-Reset)
- Clock control, PLL, power management

Device Initialization with DAvE

Debug Support and Environment Tools: Overview