Training » TriCore®: Architecture, Peripherals and Embedded Programming
TriCore®: Architecture, Peripherals and Embedded Programming
Training Objectives
You know the architecture, basic on-chip periphery and specifics of the TriCore® device family. You are able to program low-level drivers for this hardware and test them with a debugger. Moreover, you can generate interrupt and trap routines.
Required Knowledge
Knowledge of ANSI-C as well as experience with programming and the set-up of a microprocessor/microcontroller system. Knowledge of DSP is an advantage.
Contents
Infineon TriCore® Architecture: Overview
TriCore® Core
- CPU, pipelines, register sets
- Memory model, Local Memory Units, MMU, FPU
- Overview instruction set, DSP support
- On-chip bus systems
TriCore® Ports (Pin Definition and Port Functions)
Hardware-near C with Tasking Tools (spec. Data Types)
- Architecture-specific data types
- Global data handling
Programming Techniques (Periphery Description, Layer Model)
- Description of periphery
- Layer model for embedded software systems
Driver Programming (Driver Model, LLD)
- Structured driver model
- Low-level driver LLD
Protection System
Interrupt/TRAP System
Peripheral Control Processor PCP2: Overview
Direct Memory Access Controller DMA: Overview
Basic On-Chip Peripherals
- Ports, timer: STM, GPTUx, RTC
- Serial interfaces: ASCx, SSCx
External Bus Unit EBU
System Control Unit SCU, Reset, Power Management
- Start-up process
- System Control Unit (SCU)
- Resets (Power-on, HW, SW, WDT, Deep-Sleep-Reset)
- Clock control, PLL, power management
Device Initialization with DAvE
Debug Support and Environment Tools: Overview
Dates |
Price plus VAT |
Short Code |
Duration |
|
03 - 07 November 2008 |
2,050 € |
E-TRICORE |
5 days |
|
|
|||
